H8SSLASH2224 datasheet(861/1071 Pages) RENESAS

861 / 1071 page

Section 23 Clock Pulse Generator

Rev. 5.00 Aug 08, 2006 page 775 of 982

REJ09B0054-0500

Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (1)

(H8S/2258 Group)

VCC = 4.0 V to 5.5 V

Item

Symbol

Min

Max

Unit

Test Conditions

External clock input low

pulse width

tEXL

—

External clock input high

pulse width

tEXH

—

External clock rise time

tEXr

—7

External clock fall time

tEXf

—7

Figure 23.5

Note: If the duty adjustment circuit is not used, the maximum operating frequency will be lower to

match the input waveform.

(Example: If tEXL = tEXH = 37 ns and tEXr = tEXf = 7 ns, the clock cycle = 88 ns and the

maximum operating frequency = 11.3 MHz)

Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (2)

(H8S/2238B, H8S/2236B)

F-ZTAT

Masked ROM

VCC = 3.0 V to 5.5 V

VCC = 2.7 V to 5.5 V

Item

Symbol

Min

Max

Min

Max

Unit

Test

Conditions

External clock input

low pulse width

tEXL

—

External clock input

high pulse width

tEXH

—

External clock rise

time

tEXr

—7

—

External clock fall

time

tEXf

—7

—

Figure 23.5

Note: If the duty adjustment circuit is not used, the maximum operating frequency will be lower to

match the input waveform.

(Example: If tEXL = tEXH = 37 ns and tEXr = tEXf = 7 ns, the clock cycle = 88 ns and the

maximum operating frequency = 11.3 MHz)

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