H8SSLASH2224 datasheet(862/1071 Pages) RENESAS

862 / 1071 page

Section 23 Clock Pulse Generator

Rev. 5.00 Aug 08, 2006 page 776 of 982

REJ09B0054-0500

Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (3)

(H8S/2238R, H8S/2236R)

F-ZTAT

F-ZTAT and

Masked ROM

VCC = 2.7 V to 3.6 V VCC = 2.2 V to 3.6 V

Item

Symbol Min

Max

Min

Max

Unit

Test Conditions

External clock input

low pulse width

tEXL

—

External clock input

high pulse width

tEXH

—

External clock rise

time

tEXr

—

External clock fall

time

tEXf

—7

—

Figure 23.5

Note: If the duty adjustment circuit is not used, the maximum operating frequency will be lower to

match the input waveform.

(Example: If tEXL = tEXH = 37 ns and tEXr = tEXf = 7 ns, the clock cycle = 88 ns and the

maximum operating frequency = 11.3 MHz)

Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (4)

(H8S/2237 Group, H8S/2227 Group)

F-ZTAT and

Masked ROM

ZTAT

VCC =

2.7 V to 3.6 V

VCC =

2.2 V to 3.6 V

VCC =

2.7 V to 3.6 V

Item

Symbol Min

Max

Min

Max

Min

Max

Unit

Test Conditions

External clock input

low pulse width

tEXL

—

External clock input

high pulse width

tEXH

—

External clock rise

time

tEXr

—

External clock fall

time

tEXf

—

Figure 23.5

Note: If the duty adjustment circuit is not used, the maximum operating frequency will be lower to

match the input waveform.

(Example: If tEXL = tEXH = 37 ns and tEXr = tEXf = 7 ns, the clock cycle = 88 ns and the

maximum operating frequency = 11.3 MHz)

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