H8SSLASH2224 datasheet(863/1071 Pages) RENESAS

863 / 1071 page

Section 23 Clock Pulse Generator

Rev. 5.00 Aug 08, 2006 page 777 of 982

REJ09B0054-0500

Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (5)

(H8S/2239 Group)

F-ZTAT and Masked ROM

Masked ROM

VCC = 3.0 V to

3.6 V

VCC = 2.7 V to

3.6 V

VCC = 2.2 V to

3.6 V

Item

Symbol Min

Max

Min

Max

Min

Max

Unit

Test Conditions

External clock input

low pulse width

tEXL

—

31.25 —

—ns

External clock input

high pulse width

tEXH

—

31.25 —

—ns

External clock

rise time

tEXr

—

—6.25

—

External clock

fall time

tEXf

—

—6.25

—

Figure 23.5

Note: When a duty adjustment circuit is not used, maximum operating frequency is lowered

according to the input waveform.

(Example: When tEXL = tEXH = 25 ns, tEXr = tEXf = 5 ns, clock cycle time = 60 ns, and

maximum operating frequency = 16.6 MHz)

tEXH

tEXL

tEXr

tEXf

VCC × 0.5

EXTAL

Figure 23.5 External Clock Input Timing

23.2.3

Notes on Switching External Clock

When two or more external clocks (e.g.:10 MHz and 2 MHz) are used as the system clock, input

clock should be switched in software standby mode.

An example of external clock switching circuit is shown in figure 23.6. An example of external

clock switching timing is shown in figure 23.7.

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