H8SSLASH2224 datasheet(987/1071 Pages) RENESAS

987 / 1071 page

Section 27 Electrical Characteristics

Rev. 5.00 Aug 08, 2006 page 901 of 982

REJ09B0054-0500

(4) Timing of On-Chip Peripheral Modules

Table 27.33 shows the timing of on-chip peripheral modules, and table 27.34 shows the I2C bus

timing.

Table 27.33 Timing of On-Chip Peripheral Modules

Condition A (F-ZTAT version):

VCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V,

Vref = 3.6 V to AVCC, VSS = AVSS = 0 V,

φ = 32.768 kHz, 2 MHz to 13.5 MHz,

Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Condition B (Masked ROM version): VCC = 2.7 V to 5.5 V, AVCC = 3.6 V to 5.5 V,

Vref = 3.6 V to AVCC, VSS = AVSS = 0 V,

φ = 32.768 kHz, 2 MHz to 13.5 MHz,

Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Conditions A, B

Item

Symbol

Min

Max

Unit

Test Conditions

I/O port*

Output data delay time

tPWD



100

Figure 27.24

Input data setup time

tPRS



Input data hold time

tPRH



TPU

Timer output delay time

tTOCD



100

Figure 27.25

Timer input setup time

tTICS



Timer clock input setup time

tTCKS



Figure 27.26

Single edge

tTCKWH

1.5



tcyc

Timer clock

pulse width

Both edges

tTCKWL

2.5



TMR

Timer output delay time

tTMOD



100

Figure 27.27

Timer reset input setup time

tTMRS



Figure 27.29

Timer clock input setup time

tTMCS



Figure 27.28

Single edge

tTMCWH

1.5



tcyc

Timer clock

pulse width

Both edges

tTMCWL

2.5



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