H8SSLASH2224 datasheet(989/1071 Pages) RENESAS

989 / 1071 page

Section 27 Electrical Characteristics

Rev. 5.00 Aug 08, 2006 page 903 of 982

REJ09B0054-0500

Table 27.34 I2C Bus Timing

Condition A (F-ZTAT version):

VCC = 3.0 V to 5.5 V, VSS = 0 V, φ = 5 MHz to maximum

operating frequency, Ta = –20°C to +75°C

Condition B (Masked ROM version): VCC = 2.7 V to 5.5 V, VSS = 0 V, φ = 5 MHz to maximum

operating frequency, Ta = –20°C to +75°C

Conditions A, B

Item

Symbol

Min

Typ

Max

Unit

Test Conditions

SCL input cycle time

tSCL

12 tcyc



Figure 27.34

SCL input high pulse width

tSCLH

3 tcyc



SCL input low pulse width

tSCLL

5 tcyc



SCL, SDA input rise time

tSr



7.5 tcyc* ns

SCL, SDA input fall time

tSf



300

SCL, SDA input spike pulse

elimination time

tSP



1 tcyc

SDA input bus

free time

tBUF

5 tcyc



Start condition input hold

time

tSTAH

3 tcyc



Retransmission start

condition input setup time

tSTAS

3 tcyc



Stop condition input setup

time

tSTOS

3 tcyc



Data input setup time

tSDAS

0.5 tcyc



Data input hold time

tSDAH



SCL, SDA capacitive load



400

Note:

* 7.5 tcyc and 17.5 tcyc can be set according to the clock selected for use by the I

module. For details, see section 16.6, Usage Notes.

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