H8SSLASH2224 datasheet(246/1071 Pages) RENESAS

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Section 6 PC Break Controller (PBC)

Rev. 5.00 Aug 08, 2006 page 160 of 982

REJ09B0054-0500

Bit

Bit Name

Initial Value

R/W

Description

BIEA

R/W

Break Interrupt Enable

When this bit is 1, the PC break interrupt request

of channel A is enabled.

Notes: 1. Only a 0 can be written to this bit to clear the flag.

2. Read the state wherein CMFA = 1 twice or more, when the CMFA is polled after

inhibiting the PC break interruption.

3. Supported only by the H8S/2239 Group.

6.2.4

Break Control Register B (BCRB)

BCRB is the channel B break control register. The bit configuration is the same as for BCRA.

6.3

Operation

The operation flow from break condition setting to PC break interrupt exception handling is shown

in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and section 6.3.2, PC Break Interrupt

Due to Data Access, taking the example of channel A.

6.3.1

PC Break Interrupt Due to Instruction Fetch

1. Set the break address in BARA.

For a PC break caused by an instruction fetch, set the address of the first instruction byte as the

break address.

2. Set the break conditions in BCRA.

Set bit 6 (CDA) to 0 to select the CPU because the bus master must be the CPU for a PC break

caused by an instruction fetch. Set the address bits to be masked to bits 5 to 3 (BAMRA2 to 0).

Set bits 2 and 1 (CSELA1 and 0) to 00 to specify an instruction fetch as the break condition.

Set bit 0 (BIEA) to 1 to enable break interrupts.

3. When the instruction at the set address is fetched, a PC break request is generated immediately

before execution of the fetched instruction, and the condition match flag (CMFA) is set.

4. After priority determination by the interrupt controller, PC break interrupt exception handling

is started.

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