H8SSLASH2224 datasheet(247/1071 Pages) RENESAS

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Section 6 PC Break Controller (PBC)

Rev. 5.00 Aug 08, 2006 page 161 of 982

REJ09B0054-0500

6.3.2

PC Break Interrupt Due to Data Access

1. Set the break address in BARA.

For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address

space address as the break address. Stack operations and branch address reads are included in

data accesses.

2. Set the break conditions in BCRA.

Select the bus master with bit 6 (CDA). Set the address bits to be masked to bits 5 to 3

(BAMRA2 to 0). Set bits 2 and 1 (CSELA1 and 0) to 01, 10, or 11 to specify data access as the

break condition. Set bit 0 (BIEA) to 1 to enable break interrupts.

3. After execution of the instruction that performs a data access on the set address, a PC break

request is generated and the condition match flag (CMFA) is set.

4. After priority determination by the interrupt controller, PC break interrupt exception handling

is started.

6.3.3

Notes on PC Break Interrupt Handling

• When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction

PC break exception handling is executed after all data transfers have been completed and the

EEPMOV.B instruction has ended.

• When a PC break interrupt is generated at a DTC transfer address

PC break exception handling is executed after the DTC has completed the specified number of

data transfers, or after data for which the DISEL bit is set to 1 has been transferred.

6.3.4

Operation in Transitions to Power-Down Modes

The operation when a PC break interrupt is set for an instruction fetch at the address after a

SLEEP instruction is shown below.

• When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to

sleep mode, or from subactive mode to subsleep mode:

After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep

mode, and PC break interrupt handling is executed. After execution of PC break interrupt

handling, the instruction at the address after the SLEEP instruction is executed (figure 6.2 (A)).

• When the SLEEP instruction causes a transition from high speed (medium speed) mode to

subactive mode (figure 6.2 (B)).

• When the SLEEP instruction causes a transition from subactive mode to high speed (medium

speed) mode (figure 6.2 (C)).

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