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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2224 Scheda tecnica(PDF) 244 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 244 Page - Renesas Technology Corp |
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244 / 1071 page  Section 6 PC Break Controller (PBC) Rev. 5.00 Aug 08, 2006 page 158 of 982 REJ09B0054-0500 Mask control PC break interrupt Match signal Mask control BARA BCRA BARB BCRB Comparator Control logic Comparator Control logic Internal address Access status Match signal Figure 6.1 Block Diagram of PC Break Controller 6.2 Register Descriptions The PC break controller has the following registers. • Break address register A (BARA) • Break address register B (BARB) • Break control register A (BCRA) • Break control register B (BCRB) 6.2.1 Break Address Register A (BARA) BARA is a 32-bit readable/writable register that specifies the channel A break address. Bit Bit Name Initial Value R/W Description 31 to 24 Undefined Reserved These bits are read as an undefined value and cannot be modified. 23 to 0 BAA23 to BAA0 All 0 R/W Break Address 23 to 0 These bits set the channel A PC break address. |
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