H8SSLASH2224 datasheet(250/1071 Pages) RENESAS

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Section 6 PC Break Controller (PBC)

Rev. 5.00 Aug 08, 2006 page 164 of 982

REJ09B0054-0500

6.4.6

I Bit Set by LDC, ANDC, ORC, and XORC Instruction

When the I bit is set by an LDC, ANDC, ORC, and XORC instruction, a PC break interrupt

becomes valid two states after the end of the executing instruction. If a PC break interrupt is set

for the instruction following one of these instructions, since interrupts, including NMI, are

disabled for a 3-state period in the case of LDC, ANDC, ORC, and XOR, the next instruction is

always executed. For details, see section 5, Interrupt Controller.

6.4.7

PC Break Set for Instruction Fetch at Address Following Bcc Instruction

When a PC break is set for an instruction fetch at an address following a Bcc instruction:

A PC break interrupt is generated if the instruction at the next address is executed in accordance

with the branch condition, and is not generated if the instruction at the next address is not

executed.

6.4.8

PC Break Set for Instruction Fetch at Branch Destination Address of Bcc

Instruction

A PC break interrupt is generated if the instruction at the branch destination is executed in

accordance with the branch condition, and is not generated if the instruction at the branch

destination is not executed.

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