H8SSLASH2224 datasheet(258/1071 Pages) RENESAS

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Section 7 Bus Controller

Rev. 5.00 Aug 08, 2006 page 172 of 982

REJ09B0054-0500

7.3.4

Bus Control Register H (BCRH)

BCRH selects enabling or disabling of idle cycle insertion, and the memory interface for area 0.

Bit

Bit Name

Initial Value R/W

Description

ICIS1

R/W

Idle Cycle Insert 1

Selects whether or not one idle cycle state is to be

inserted between bus cycles when successive external

read cycles are performed in different areas.

0: Idle cycle not inserted in case of successive external

read cycles in different areas

1: Idle cycle inserted in case of successive external read

cycles in different areas

ICIS0

R/W

Idle Cycle Insert 0

Selects whether or not one idle cycle state is to be

inserted between bus cycles when successive external

read and write cycles are performed.

0: Idle cycle not inserted in case of successive external

read and write cycles

1: Idle cycle inserted in case of successive external read

and write cycles

BRSTRM

R/W

Burst ROM enable

Selects whether area 0 is used as a burst ROM

interface.

0: Area 0 is basic bus interface

1: Area 0 is burst ROM interface

BRSTS1

R/W

Burst Cycle Select 1

Selects the number of burst cycles for the burst ROM

interface.

0: Burst cycle comprises 1 state

1: Burst cycle comprises 2 states

BRSTS0

R/W

Burst Cycle Select 0

Selects the number of words that can be accessed in a

burst ROM interface burst access.

0: Max. 4 words in burst access

1: Max. 8 words in burst access

2 to

—

All 0

R/W

Reserved

The write value should always be 0.

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