H8SSLASH2224 datasheet(259/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 7 Bus Controller

Rev. 5.00 Aug 08, 2006 page 173 of 982

REJ09B0054-0500

7.3.5

Bus Control Register L (BCRL)

BCRL performs selection of the external bus-released state protocol, and enabling or disabling of

WAIT pin input.

Bit

Bit Name

Initial Value R/W

Description

BRLE

R/W

Bus release enable

Enables or disables external bus release.

0: External bus release is disabled.

BREQ and BACK

can be used as I/O ports

1: External bus release is enabled

6—

R/W

Reserved

The write value should always be 0.

5—

—

Reserved

This bit is always read as 0 and cannot be modified.

4—

R/W

Reserved

The write value should always be 0.

3—

R/W

Reserved

The write value should always be 1.

2, 1 —

All 0

R/W

Reserved

The write value should always be 0.

WAITE

R/W

WAIT pin enable

Selects enabling or disabling of wait input by the

WAIT

pin.

0: Wait input by

WAIT pin disabled. WAIT pin can be

used as I/O port

1: Wait input by

WAIT pin enabled

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