H8SSLASH2224 datasheet(263/1071 Pages) RENESAS

263 / 1071 page

Section 7 Bus Controller

Rev. 5.00 Aug 08, 2006 page 177 of 982

REJ09B0054-0500

Table 7.2

Bus Specifications for Each Area (Basic Bus Interface)

ABWCR

ASTCR

WCRH, WCRL

Bus Specifications (Basic Bus Interface)

ABWn

ASTn

Wn1

Wn0

Bus Width Number of Access

States

Number of Program

Wait States



7.4.3

Bus Interface for Each Area

The initial state of each area is basic bus interface, 3-state access space. The initial bus width is

selected according to the operating mode. The bus specifications described here cover basic items

only, and the sections on each memory interface (7.6, Basic Bus Interface and 7.7, Burst ROM

Interface) should be referred to for further details.

(1) Area 0: Area 0 includes on-chip ROM, and in ROM-disabled extended mode, all of area 0 is

external space. In ROM-enabled extended mode, the space excluding on-chip ROM is external

space.

When area 0 external space is accessed, the

CS0 signal can be output.

Either basic bus interface or burst ROM interface can be selected for area 0.

(2) Areas 6 to 1: In external extended mode, all of areas 6 to 1 is external space. When area 6 to 1

external space is accessed, the

CS6 to CS1 pin signals respectively can be output. Only the

basic bus interface can be used for areas 6 to 1.

(3) Area 7: Area 7 includes the on-chip RAM and internal l/O registers. In external extended

mode, the space excluding the on-chip RAM and internal l/O registers, is external space. The

on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to

1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding

space becomes external space.

When area 7 external space is accessed, the

CS7 signal can be output.

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