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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2224 Scheda tecnica(PDF) 301 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 301 Page - Renesas Technology Corp |
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301 / 1071 page  Section 8 DMA Controller (DMAC) Rev. 5.00 Aug 08, 2006 page 215 of 982 REJ09B0054-0500 • DMACR_0B and DMACR_1B Bit Bit Name Initial Value R/W Description 7 0R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 6 5 DAID DAIDE 0 0 R/W R/W Destination Address Increment/Decrement Destination Address Increment/Decrement Enable These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. 00: MARB is fixed 01: MARB is incremented after a data transfer • When DTSZ = 0, MARB is incremented by 1 • When DTSZ = 1, MARB is incremented by 2 10: MARB is fixed 11: MARB is decremented after a data transfer • When DTSZ = 0, MARB is decremented by 1 • When DTSZ = 1, MARB is decremented by 2 4— 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. |
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