H8SSLASH2224 datasheet(305/1071 Pages) RENESAS

305 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 219 of 982

REJ09B0054-0500

Bit

Bit Name

Initial Value

R/W

Description

DTA1B

DTA1A

DTA0B

DTA0A

R/W

Data Transfer Acknowledge 1B

Data Transfer Acknowledge 1A

Data Transfer Acknowledge 0B

Data Transfer Acknowledge 0A

These bits enable or disable clearing when

DMA transfer is performed for the internal

interrupt source selected by the DTF3 to DTF0

bits in DMACR.

It the DTA bit is set to 1 when DTE = 1, the

internal interrupt source is cleared automatically

by DMA transfer. When DTE = 1 and DTA = 1,

the internal interrupt source does not issue an

interrupt request to the CPU or DTC.

If the DTA bit is cleared to 0 when DTE = 1, the

internal interrupt source is not cleared when a

transfer is performed, and can issue an interrupt

request to the CPU or DTC in parallel. In this

case, the interrupt source should be cleared by

the CPU or DTC transfer.

When DTE = 0, the internal interrupt source

issues an interrupt request to the CPU or DTC

regardless of the DTA bit setting.

0: Clearing is disabled when DMA transfer is

performed for the selected internal interrupt

source

1: Clearing is enabled when DMA transfer is

performed for the selected internal interrupt

source

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