H8SSLASH2224 datasheet(304/1071 Pages) RENESAS

304 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 218 of 982

REJ09B0054-0500

8.3.5

DMA Band Control Registers H and L (DMABCRH and DMABCRL)

DMABCR controls the operation of each DMAC channel. The bit functions in the DMACR

registers differ according to the transfer mode.

(1) Short Address Mode

• DMABCRH

Bit

Bit Name

Initial Value

R/W

Description

FAE1

R/W

Full Address Enable 1

Specifies whether channel 1 is to be used in

short address mode or full address mode. In

short address mode, channels 1A and 1B can

be used as independent channels.

0: Short address mode

1: Full address mode

FAE0

R/W

Full Address Enable 0

Specifies whether channel 0 is to be used in

short address mode or full address mode. In

short address mode, channels 0A and 0B can

be used as independent channels.

0: Short address mode

1: Full address mode

SAE1

R/W

Single Address Enable 1

Specifies whether channel 1B is to be used for

transfer in dual address mode or single address

mode. This bit is invalid in full address mode.

0: Dual address mode

1: Single address mode

SAE0

R/W

Single Address Enable 0

Specifies whether channel 0B is to be used for

transfer in dual address mode or single address

mode. This bit is invalid in full address mode.

0: Dual address mode

1: Single address mode

H8S/2224 Scheda tecnica(PDF) 304 Page - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 304 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL