H8SSLASH2224 datasheet(325/1071 Pages) RENESAS

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Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 239 of 982

REJ09B0054-0500

8.5.3

Idle Mode

Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In

idle mode, one byte or word is transferred in response to a single transfer request, and this is

executed the number of times specified in ETCR. One address is specified by MAR, and the other

by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 8.6

summarizes register functions in idle mode.

Table 8.6

Function

DTDIR = 0 DTDIR = 1 Initial Setting

Operation

MAR

Source

address

Destination

address

Start address of

transfer destination

or transfer source

Fixed

IOAR

H'FF

Destination

address

Source

address

Start address of

transfer source or

transfer destination

Fixed

ETCR

Transfer counter

Number of transfers Decremented every

transfer; transfer

ends when count

reaches H'0000

MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is

neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the

other address. The upper 8 bits of IOAR have a value of H'FF.

Figure 8.5 illustrates operation in idle mode.

Transfer

IOAR

1 byte or word transfer performed in

response to 1 transfer request

MAR

Figure 8.5 Operation in Idle Mode

The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a

transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer

ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The

maximum number of transfers, when H'0000 is set in ETCR, is 65,536.

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