H8SSLASH2224 datasheet(323/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

Logo

323 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 237 of 982

REJ09B0054-0500

Address T

Address B

Transfer

IOAR

1 byte or word transfer performed in

response to 1 transfer request

Legend:

Address T = L

Address B = L + ( 1)DTID (2DTSZ (N

1))

Where :

L = Value set in MAR

N = Value set in ETCR

Figure 8.3 Operation in Sequential Mode

The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a

data transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data

transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or

DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.

Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external

requests, SCI transmit-data-empty and receive-data-full interrupts, and TPU channel 0 to 5

compare match/input capture A interrupts. External requests can only be specified for channel B.

Figure 8.4 shows an example of the setting procedure for sequential mode.

H8S/2224 Scheda tecnica(PDF) 323 Page - Renesas Technology Corp