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7480 Group and 7481 Group User's Manual

1-47

HARDWARE

1.11 Interrupts

1.11.3 Interrupt Sources

In the 7480 Group and 7481 Group, the interrupt requests can be generated by 14 sources (5 external,

8 internal, and 1 software).

The interrupts are vectored interrupts whose priority levels are fixed, and each interrupt has its own priority

level. When two or more interrupt requests are generated at the same sampling time, which is a timing to

test the generation of interrupt requests, the interrupt with a higher priority is acceptable.

For the priority levels of interrupts, refer to Table 1.11.1 Interrupt Sources.

Each interrupt source is described below.

(1)

INT0 and INT1 Interrupts

When a rising edge or a falling edge of the input signal to the INT0 or INT1 pin is detected, an

interrupt request is generated.

The edge polarity to be detected can be selected by the INT0 edge selection bit or the INT1 edge

selection bit of the edge polarity selection register.

The request bit, the enable bit, and the interrupt vector of the INT1 interrupt have the alternative

functions of those of the key-on wakeup interrupt respectively. When the INT1 interrupt is used, clear

the INT1 source selection bit at the STP/WIT of the edge polarity selection register to ‘0’.

• State after system is released from reset

After system is released from reset, the INT0 edge selection bit, INT1 edge selection bit and the

INT1 source selection bit at the STP/WIT of the edge polarity selection register are all cleared to

‘0’.

In such conditions, though an interrupt request is generated by detecting a falling edge of the INT0

or INT1 pin, the interrupt request cannot be accepted because the corresponding interrupt enable

bit is ‘0’ and the interrupt disable flag is ‘1’.

Notes 1: The INT0 and INT1 pins have the alternative functions of input port pins P30 and P31,

respectively. When these pins are used as input port pins, valid edges can still be detected

because the 7480 Group and 7481 Group does not have the function to switch the INT pins

to input port pins. Therefore, when these pins are used as input port pins, clear all the

corresponding interrupt enable bits to ‘0’ (disabled).

2: Keep the trigger width input to the INT pins 250 ns or more.

(2)

Key-On Wakeup Interrupt

When the INT1 source selection bit at the STP/WIT of the edge polarity selection register is ‘1’ and

the LOW level is applied to any pin of port P0 which is used as input in the stop/wait mode at the

execution of STP/WIT, a key-on wakeup interrupt request is generated. In other states than the stop/

wait mode, the key-on wakeup interrupt is invalid.

The request bit, the enable bit, and the interrupt vector of the key-on wakeup interrupt have the

alternative functions of those of the INT1 interrupt respectively. When the key-on wakeup interrupt

is used, set the INT1 source selection bit at the STP/WIT of the edge polarity selection register to

‘1’.

Note: When the key-on wakeup interrupt is used, execute the STP/WIT instruction after all inputs to

port P0 are held HIGH. If the LOW level is applied to any input pin of port P0, an execution

of the STP/WIT instruction generates an interrupt request instantly.

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