7480 datasheet(98/337 Pages) RENESAS

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7480 Group and 7481 Group User's Manual

1-81

1.12 Timer X and Timer Y

HARDWARE

Generation of Programmable Waveform

When an underflow occurs in a timer, the contents of the output level latches of the timer X or Y

mode register are output from the following pins ( in Figure 1.12.18):

• CNTR0 pin (Timer X used)

• CNTR1 pin (Timer Y used)

When the timer X or Y operation mode bits of the timer X or Y mode register, which are set to other

modes, are switched to the programmable waveform generation mode, the CNTR pin outputs are

initialized to LOW ( in Figure 1.12.18).

Figure 1.12.18 Operation Example in Programmable Waveform Generation Mode

Count source

000016

Timer X stop

control bit

‘0’ is

written

Time

Timer X interrupt

request bit

CNTR0 pin output

Output level latch

Writing to timer

X(Note 1)

‘1’ is

written

Initialized to LOW when setting

timer X operation mode bits

Change of timer X

(Note 2)

INT0 pin input

(Note 4)

INT0

interrupt request bit

Notes 1: In this case, timer X write control bit is ‘0’ (writing to timer and timer latch simultaneously).

2: In this case, timer X write control bit is ‘1’ (writing to only timer latch).

3: In this case, timer X trigger selection bit is ‘1’ (trigger occurs, at the same time, timer X is activated ).

4: In this case, INT0 edge selection bit is ‘1’ (rising edge is valid).

: Setting value to timer X

: Contents of timer latch is reloaded

: Underflow

: Pulse width

: Clearing by writing ‘0’ to interrupt request bit or accepting interrupt request

H(s) =

Count source frequency × (Setting value to timer X+1)

‘0’ is

written

‘0’ is

written

‘1’ is

written

‘1’ is

written

(Note 3)

Count start

Undefined

Change of timer X

(Note 2)

Undefined

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