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7480 Group and 7481 Group User's Manual

1-83

1.12 Timer X and Timer Y

HARDWARE

Figure 1.12.20 Setting of Programmable Waveform Generation Mode (2)

Notes 5: When bit 5 of timer mode register is ‘1’,

timer count does not start at this time.

Trigger (input signal of INT pin) occurs,

at the same time, timer count starts.

Notes 6: Keep the trigger width input to INT pin 250 ns

or more.

Timer X count value is set

Procedure 4 Setting timer (Note 4)

Timer X low-order (TXL) [Address 00F016]

• when timer X is used

Timer X high-order (TXH) [Address 00F116]

Timer Y count value is set

Timer Y low-order (TYL) [Address 00F216]

• when timer Y is used

Timer Y high-order (TYH) [Address 00F316]

Notes 4: When writing to timer, set the low-order byte

and high-order byte in this order.

Timer XY control register (TXYCON) [Address 00F816]

Timer X count start (when timer X is used)

Timer Y count start (when timer Y is used)

Procedure 5 Start of timer count (Note 5)

Programmable waveform generation mode (Note 3)

Timer Y write control

0: Writing to latch and timer simultaneously

1: Writing to only latch

Timer Y mode register (TYM) [Address 00F716]

• when timer Y is used

Timer Y count source selection

00: f(XIN)/2

01: f(XIN)/8

10: f(XIN)/16

11: Not available

Output level latch

Timer Y trigger selection

0: Timer Y free run

1: Trigger occurrence (input signal of INT1 pin) and timer Y start

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