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7480 Scheda tecnica(PDF) 78 Page - Renesas Technology Corp |
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7480 Scheda tecnica(HTML) 78 Page - Renesas Technology Corp |
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78 / 337 page ![]() 1-61 1.12 Timer X and Timer Y HARDWARE 7480 Group and 7481 Group User's Manual Figure 1.12.4 Timer Y Timer Y (Timer Y latch) b5 b6 b7 b4 b3 b2 b1 b0 b Function At reset 1 2 3 4 5 6 7 0 1 Timer Y (high-order) (TYH) [Address 00F316] b5 b6 b7 b4 b3 b2 b1 b0 Timer Y (low-order) (TYL) [Address 00F216] The low-order count value of timer Y is indicated. b 1 2 3 4 5 6 7 0 The high-order count value of timer Y is indicated. Notes 1: Do not write to these bits in pulse period measurement mode or pulse width measurement mode. 2: When b3 of timer Y mode register is ‘0’, writing to latch and timer is simultaneously performed. When b3 is ‘1’, writing to only latch is performed. 3: When reading/writing from/to timer Y, read/write from/to both high-order and low-order bytes. At reading, read the high-order byte and the low-order byte in this order. At writing, write the low-order byte and the high-order byte in this order. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Function At reset RW O O O O O O O O Note 1 RW O O O O O O O O Note 1 |
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