7480 datasheet(85/337 Pages) RENESAS

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1-68

1.12 Timer X and Timer Y

HARDWARE

7480 Group and 7481 Group User's Manual

(2)

Setting of Timer Mode and Event Count Mode

Figures 1.12.9 and 1.12.10 show the setting of the timer mode and the event count mode.

Figure 1.12.9 Setting of Timer Mode and Event Count Mode (1)

Timer X count stop (when timer X is used)

Timer Y count stop (when timer Y is used)

Procedure 1 Stop of timer count

Timer XY control register (TXYCON) [Address 00F816]

Timer • event counter mode

Timer X write control

0: Writing to latch and timer simultaneously

1: Writing to only latch

Procedure 3 Setting timer mode register

Timer X mode register (TXM) [Address 00F616]

• when timer X is used

Timer X count source selection

00: f(XIN)/2

01: f(XIN)/8

10: f(XIN)/16

11: CNTR0 pin input

in timer mode

in event count mode

Timer • event count mode

Timer Y write control

0: Writing to latch and timer simultaneously

1: Writing to only latch

Timer Y mode register (TYM) [Address 00F716]

• when timer Y is used

Timer Y count source selection

00: f(XIN)/2

01: f(XIN)/8

10: f(XIN)/16

11: CNTR1 pin input

in timer mode

in event count mode

: ‘Not implemented’.

Notes 1: In the 7480 Group, these bits are not implemented.

Port P40 input mode (when timer X is used)

Port P41 input mode (when timer Y is used)

Port P4 direction register (P4D) [Address 00C916]

Procedure 2 Setting CNTR pin input in event counter mode

1. Setting port pin which has the alternative function of CNTR pin to input mode

CNTR0 edge porality selection (when timer X is used)

CNTR1 edge porality selection (when timer Y is used)

0: CNTR pin input is used as the count source.

1: The inverted CNTR pin input is used as the count source.

Edge porality selection register (EG) [Address 00D416]

2. Setting edge porality selection register

(Note 1)

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