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1.12 Timer X and Timer Y

HARDWARE

7480 Group and 7481 Group User's Manual

1.12.5 Pulse Output Mode

(1)

Operations in Pulse Output Mode

Operations in the pulse output mode are explained with Figure 1.12.11.

Count Sources

In the pulse output mode, timer X or timer Y can select the following count sources with the timer

X or Y count source selection bits:

• f(XIN)/2

• f(XIN)/8

• f(XIN)/16

Writes to and Reads from Timers

When ‘TL (000016 through FFFF16)’ is written to a timer, the following different operations are

performed depending on the state of the timer X or Y write control bit:

• In the ‘0’ state of the timer X or Y write control bit, the ‘TL’ is set in both the timer latch and the

timer ( in Figure 1.12.11).

• In the ‘1’ state of the timer X or Y write control bit, the ‘TL’ is set in the timer latch only.

Also, the contents of the timer can be read by a read operation.

Count Operation

• When the timer X or Y stop control bit is cleared to ‘0’, the timer starts counting ( in Figure

1.12.11).

• When the timer X or Y stop control bit is set to ‘1’, the timer stops counting ( in Figure 1.12.11).

In the count operation, the contents of each timer are decremented by 1 at every rising edge of the

count source ( in Figure 1.12.11).

Reloading Timers

When a timer reaches ‘000016’ in the count operation, an underflow occurs at the subsequent rising

edge of the count source, and the contents of the timer latch are reloaded to the timer ( in Figure

1.12.11).

Timer Interrupt

At an underflow, the timer X or Y interrupt request bit is set to ‘1’; then a timer interrupt request is

generated ( in Figure 1.12.11).

Pulse Output

At every underflows, polarity-inverted pulses are output from the following pins ( in Figure 1.12.11):

• CNTR0 pin (Timer X used)

• CNTR1 pin (Timer Y used)

When the timer X or Y write control bit is ‘0’, the CNTR pin output is initialized to the following levels

by a write to the timer:

• HIGH when the CNTR edge selection bit is ‘0’ ( in Figure 1.12.11).

• LOW when the CNTR edge selection bit is ‘1’.

Notes 1: When the timer X or Y write control bit is ‘1’, the CNTR pin output level cannot be initialized

by a write to the timer.

2: In the pulse output mode, the output level of a CNTR pin is inverted when the CNTR edge

selection bit is switched ( in Figure 1.12.11).

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