7480 datasheet(68/337 Pages) RENESAS

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7480 Group and 7481 Group User's Manual

1-51

HARDWARE

1.11 Interrupts

Processing Before Interrupt Service Routine

When an interrupt request is accepted, the interrupt service routine is started after the following are

performed.

the instruction being executed at the generation of the interrupt request is completed

the pipeline postprocessing

the pushing onto the stack, and vector fetch

Figure 1.11.9 shows the processing time from the interrupt generation until the execution of an interrupt

service routine, and Figure 1.11.10 shows a timing at interrupt acceptance.

Figure 1.11.9 Processing Time from Interrupt Generation until Execution of Interrupt Service Routine

Figure 1.11.10 Timing at Interrupt Acceptance

Waiting time for

pipeline

postprocessing

Main routine

Push onto stack

Vector fetch

Interrupt service

routine

Interrupt request is generated

Interrupt service routine starts

2 cycles

5 cycles

Note: At the DIV instruction executed.

7 to 23 cycles

(At internal system clock

φ = 4 MHz, 1.75 µs to 5.75 µs)

0 to 16 cycles (Note)

Waiting time for

pipeline

postprocessing

Push onto stack

Vector fetch

Interrupt service routine starts

SYNC

Address bus

Data bus

SYNC:

BL, BH:

AL, AH:

SPS:

CPU operation code fetch cycle

(This is an internal signal which cannot be examined from the external.)

Vector address of each interrupt

Jump address of each interrupt

‘0016’ or ‘0116’

(when the stack page selection bit is ‘0’, SPS is ‘0016’, and when the bit is ‘1’, SPS is ‘0116’)

S, SPS

S-1, SPS S-2, SPS

AL, AH

Not used

PCH

PCL

R/W

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