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7480 Scheda tecnica(PDF) 114 Page - Renesas Technology Corp |
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7480 Scheda tecnica(HTML) 114 Page - Renesas Technology Corp |
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114 / 337 page ![]() 7480 Group and 7481 Group User's Manual 1-97 HARDWARE 1.13 Timer 1 and Timer 2 (2) Timer 1 Mode Register and Timer 2 Mode Register These registers consist of the bits controlling the operation of timer 1 and timer 2. Figures 1.13.5 and 1.13.6 show the timer 1 and 2 mode registers. Figure 1.13.5 Timer 1 Mode Register Figure 1.13.6 Timer 2 Mode Register Timer 2 mode register b5 b6 b7 b4 b3 b2 b1 b0 b Name Function At reset 1 2 3 4 5 6 7 00 0 0 0 0 0 0 0 Timer 2 mode register (T2M) [Address 00FA16] Timer 2 stop control bit Timer 2 operation mode bit Output level latch Timer 2 count source selection bits 0 : Count operation 1 : Count stop 0 : Timer mode 1 : Programmable waveform generation mode b7 b6 0 0 : f(XIN)/8 0 1 : f(XIN)/64 1 0 : f(XIN)/128 1 1 : f(XIN)/256 Not implemented. Writing to these bits is disabled. These bits are ‘0’ at reading. Not implemented. Writing to this bit is disabled. This bit is ‘0’ at reading. 0 : LOW output from T1 pin 1 : HIGH output from T1 pin 00 0 RW 0 0 O O × × O O O O 0 × OO O O Timer 1 mode register b5 b6 b7 b4 b3 b2 b1 b0 b Name Function At reset 1 2 3 4 5 6 7 00 0 0 0 0 0 0 0 Timer 1 mode register (T1M) [Address 00F916] Timer 1 stop control bit Timer 1 operation mode bit Output level latch Timer 1 count source selection bits 0 : Count operation 1 : Count stop 0 : Timer mode 1 : Programmable waveform generation mode b7 b6 Not implemented. Writing to these bits is disabled. These bits are ‘0’ at reading. Not implemented. Writing to this bit is disabled. This bit is ‘0’ at reading. 0 0 : f(XIN)/8 0 1 : f(XIN)/64 1 0 : f(XIN)/128 1 1 : f(XIN)/256 0 : LOW output from T0 pin 1 : HIGH output from T0 pin 00 0 RW 0 0 O O × × O O O O 0 × OO O O |
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