7480 datasheet(157/337 Pages) RENESAS

157 / 337 page

7480 Group and 7481 Group User's Manual

1-140

HARDWARE

(3)

Setting of Bus Arbitration Interrupt

Figure 1.14.26 shows the setting of bus arbitration interrupt.

Figure 1.14.26 Setting of Bus Arbitration Interrupt

1.14 Serial I/O

Serial I/O receive interrupt disabled

Serial I/O transmit interrupt disabled

Procedure 1 Disabling of the acceptance of the interrupts associated serial I/O

Interrupt control register 1 (ICON1) [Address 00FE16]

Bus arbitration interrupt disabled

Procedure 2 Setting serial I/O full-duplex communication

Bus collision detect enabled

Procedure 3 Setting bus collision detection control register

Bus collision detection control register (BUSARBCON) [Address 00E516]

There is no serial I/O receive interrupt request

There is no serial I/O transmit interrupt request

Procedure 4 Setting the using interrupt request bit to ‘0’

Interrupt request register 1 (IREQ1) [Address 00FC16]

There is no bus arbitration interrupt request

Serial I/O receive interrupt enabled

Serial I/O transmit interrupt enabled

Procedure 5 Enabling the acceptance of the using interrupts

Interrupt control register 1 (ICON1) [Address 00FE16]

Bus arbitration interrupt enabled

Procedure 6 Writing transmit data into transmit buffer register

1. Set Baud Rate Generator when the divided BRG output/4 or 16 is selected as the synchronous clock.

2. Set Serial I/O Control Register (in full-duplex communication).

3. Set UART Control Register (in UART).

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