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7480 Scheda tecnica(PDF) 174 Page - Renesas Technology Corp |
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7480 Scheda tecnica(HTML) 174 Page - Renesas Technology Corp |
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174 / 337 page ![]() 7480 Group and 7481 Group User's Manual 1-157 HARDWARE 1.17.3 Notes on Usage Pay attention to the following notes when reset is used. Internal clock φ becomes f(XIN)/2 (high-speed mode) when the system is released from reset. Timer 1 and timer 2 are counting when the system is released from reset. Apply 0.32 V or less to the RESET pin at the time that power source voltage passes 2.7V, at power on. When the STP instruction is executed in normal operations, I/O port pins retain the states immediately before internal clock φ stops. If the CPU is then forced to the reset state from the stop mode, the I/O pins go to the input mode with the high-impedance state. 1.17 Reset |
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