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7480 Group and 7481 Group User's Manual

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1.19 Power Saving Function

HARDWARE

1.19.1 Registers Associated with Power Saving

Figure 1.19.2 shows the memory map of the registers associated with power saving.

Figure 1.19.2 Memory Map of Registers Associated with Power Saving

(1)

STP Instruction Operation Control Register

The STP instruction operation control register has only one bit that selects the valid/invalid of the

STP and the WIT instruction.

Figure 1.19.3 shows the STP instruction operation control register.

Figure 1.19.3 STP Instruction Operation Control Register

00D416

00DE16

Edge polarity selection register (EG)

STP instruction operation control register (STPCON)

STP instruction operation control register

b4 b3 b2 b1 b0

Function

At reset

STP instruction operation control register (STPCON) [Address 00DE16]

STP and WIT valid/invalid

selection bit (Note)

Name

0 : STP/WIT instruction valid

1 : STP/WIT instruction invalid

Not implemented.

Writing to these bits is disabled.

These bits are ‘0’ at reading.

Note: The STP and WIT instructions are invalid after the system is released from reset. When

using these instructions, set STP and WIT valid/invalid selection bit of the STP instruction

operation control register to ‘1’, then set this bit to ‘0’. (Writing twice successively)

When not using the STP and WIT instructions, set this bit to ‘1’ either once or twice.

00 000 00

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