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7480 Scheda tecnica(PDF) 232 Page - Renesas Technology Corp |
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7480 Scheda tecnica(HTML) 232 Page - Renesas Technology Corp |
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232 / 337 page ![]() 7480 Group and 7481 Group User's Manual 2-17 APPLICATIONS Figure 2.2.19 Phase Control Procedure Example 2.2 Timer X and Timer Y Initialize RESET(Note 1) 0 SEI 10 ×× 0 11 1 CLI INT1 interrupt service routine Change timer Y (Note 3) RTI Processing Processing b0 b7 b0 b7 Set timer Y mode register TYM(Address 00F716) Programmable one-shot output mode Writing to latch only Timer Y ← Initial value (Note 3) Port P41 (alternative function of CNTR1) is set to output. INT1 edge selection bit ← 1 (rising edge detected) CNTR1 edge selection bit ← 0 (Note 2) Timer Y count source : f(XIN)/16 Port P41 (alternative function of CNTR1) ← LOW Notes 1: State after system is released from reset • Timer Y stop control bit = 0 (count stop) • Timer Y interrupt enable bit = 0 (disabled) 2: HIGH level one-shot pulse is output. 3: Write to timer Y in order of low-order to high-order byte. INT1 interrupt request bit ← 0 INT1 interrupt enable bit ← 1 Phase control processing • Period of feedback signal measured • Measured value analyzed (determination of timer Y setting value) Set timer XY control register TXYCON(Address 00F816) Timer Y count start |
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