7480 datasheet(243/337 Pages) RENESAS

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7480 Group and 7481 Group User's Manual

2-28

APPLICATIONS

2.3 Serial I/O

Figure 2.3.14 Control Procedure Example (2) of LAN Communications

RTI

Serial I/O receive interrupt service routine

RTI

Bus arbitration interrupt service routine

RTI

CNTR0 interrupt service routine (when receiving)

RTI

Bus arbitration interrupt enable bit

← 0

Timer 1 interrupt service routine

RTI

Serial I/O transmit interrupt service routine

When transmitting

Write the following transmit data to transmit buffer

1. Priority code

2. Target ID

3. Source ID

4. Data

5. CRC code

In the interrupt processing after writing transmit data

to transmit buffer register is completed, change

transmit interrupt source to ‘when transmit shift

operation is completed’, and the interrupt source is

back to the state before changing at the next interrupt

processing.

When receiving

Write dummy data to transmit buffer register

When SOF collision occurs, transmit processing is

stopped and receive processing is started from

priority code.

When priority code collision occurs,

transmit processing is stopped and receive

processing is started from target ID.

When data collision occurs, communication error on

communication line is detected, transmit processing is

stopped, and processing against error such as re-

transmission is performed.

When SOF is received

• Write dummy data to transmit buffer register for

generating synchronous clock

• Acceptance of timer 1 interrupt request is disabled

Processing for EOD, EOF and IFS waiting time elapse

When transmitting

Transmit data is received

When RSP code is received

When receiving

Read receive buffer register

1. Priority code

2. Target ID

3. Source ID

4. Data

5. CRC code

Level of RxD pin is checked every 3-byte reception

• HIGH level: next data is received

• LOW level: EOD is detected

When rising edge is detected

• CNTR0 edge selection bit

← 0

(falling edge detected)

• HIGH width is measured with timer X

When falling edge is detected

• CNTR0 edge selection bit

← 1

(rising edge detected)

• LOW width is measured with timer X

• SOF LOW width waiting time is generated with

timer 1 (acceptance of timer 1 interrupt request

is enabled)

Reception is completed when SOF is not received

correctly.

Note: Write ‘0016’ as dummy data to transmit buffer register.

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