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7480 Scheda tecnica(PDF) 277 Page - Renesas Technology Corp |
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7480 Scheda tecnica(HTML) 277 Page - Renesas Technology Corp |
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277 / 337 page ![]() 3-12 3.1 Control Registers APPENDICES 7480 Group and 7481 Group User's Manual Figure 3.1.17 Timer X Timer X (Timer X latch) b5 b6 b7 b4 b3 b2 b1 b0 b Function At reset 1 2 3 4 5 6 7 0 1 Timer X (high-order) (TXH) [Address 00F116] b5 b6 b7 b4 b3 b2 b1 b0 Timer X (low-order) (TXL) [Address 00F016] The low-order count value of timer X is indicated. b Function At reset 1 2 3 4 5 6 7 0 The high-order count value of timer X is indicated. Notes 1: Do not write to these bits in pulse period measurement mode or pulse width measurement mode. 2: When b3 of timer X mode register is ‘0’, writing to latch and timer is simultaneously performed. When b3 is ‘1’, writing to only latch is performed. 3: When reading/writing from/to timer X, read/write from/to both high-order and low-order bytes. At reading, read the high-order byte and the low-order byte in this order. At writing, write the low-order byte and the high-order byte in this order. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RW O O O O O O O O RW O O O O O O O O Note 1 Note 1 |
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