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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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ATtiny261-ESSZ Scheda tecnica(PDF) 124 Page - ATMEL Corporation |
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ATtiny261-ESSZ Scheda tecnica(HTML) 124 Page - ATMEL Corporation |
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124 / 227 page  124 7753C–AVR–07/09 ATtiny261/ATtiny461/ATtiny861 16.11.8 OCR1A – Timer/Counter1 Output Compare Register A The output compare register A is an 8-bit read/write register. The Timer/Counter Output Compare Register A contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and OCR1A to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow- ing the compare event. Note that, if 10-bit accuracy is used special procedures must be followed when accessing the internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are described in section “Accessing 10-Bit Registers” on page 112. 16.11.9 OCR1B – Timer/Counter1 Output Compare Register B The output compare register B is an 8-bit read/write register. The Timer/Counter Output Compare Register B contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow- ing the compare event. Note that, if 10-bit accuracy is used special procedures must be followed when accessing the internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are described in section “Accessing 10-Bit Registers” on page 112. 16.11.10 OCR1C – Timer/Counter1 Output Compare Register C The output compare register C is an 8-bit read/write register. The Timer/Counter Output Compare Register C contains data to be continuously compared with Timer/Counter1, and a compare match will clear TCNT1. This register has the same function in Normal mode and PWM modes. Bit 76543210 0x2D (0x4D) MSB LSB OCR1A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000 Bit 76543210 0x2C (0x4C) MSB LSB OCR1B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000 Bit 76543210 0x2B (0x4B) MSB LSB OCR1C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 11111111 |
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