AM186EM-33VCSLASHW datasheet(28/98 Pages) AMD

28 / 98 page

Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINA R Y

Interrupt requests are synchronized internally, and can

be edge-triggered or level-triggered. To guarantee in-

terrupt recognition, the requesting device must con-

tinue asserting INT3 until the request is acknowledged.

INT3 becomes INTA1 when INT1 is configured in cas-

cade mode.

INTA1—When the microcontroller interrupt control unit

is operating in cascade mode or special fully-nested

mode, this pin indicates to the system that the micro-

controller needs an interrupt type to process the inter-

rupt request on INT1. In both modes, the peripheral

issuing the interrupt request must provide the micro-

controller with the corresponding interrupt type.

IRQ—When the microcontroller interrupt control unit is

operating as a slave to an external master interrupt

controller, this pin lets the microcontroller issue an in-

terrupt request to the external master interrupt control-

ler.

INT4/PIO30

Maskable Interrupt Request 4 (input,

asynchronous)

This pin indicates to the microcontroller that an inter-

rupt request has occurred. If the INT4 pin is not

masked, the microcontroller then transfers program ex-

ecution to the location specified by the INT4 vector in

the microcontroller interrupt vector table.

Interrupt requests are synchronized internally, and can

be edge-triggered or level-triggered. To guarantee in-

terrupt recognition, the requesting device must con-

tinue asserting INT4 until the request is acknowledged.

LCS/ONCE0

Lower Memory Chip Select (output, synchronous,

internal pullup)

ONCE Mode Request 0 (input)

LCS—This pin indicates to the system that a memory

access is in progress to the lower memory block. The

base address and size of the lower memory block are

programmable up to 512 Kbytes. LCS is held High dur-

ing a bus hold condition.

ONCE0—During reset this pin and ONCE1 indicate to

the microcontroller the mode in which it should operate.

ONCE0 and ONCE1 are sampled on the rising edge of

RES. If both pins are asserted Low, the microcontroller

enters ONCE mode; otherwise, it operates normally.

In ONCE mode, all pins assume a high-impedance

state and remain in that state until a subsequent reset

occurs. To guarantee that the microcontroller does not

inadvertently enter ONCE mode, ONCE0 has a weak in-

ternal pullup resistor that is active only during reset. This

pin is not three-stated during a bus hold condition.

MCS3/RFSH/PIO25

Midrange Memory Chip Select 3

(output, synchronous, internal pullup)

Automatic Refresh (output, synchronous)

MCS3—This pin indicates to the system that a memory

access is in progress to the fourth region of the

midrange memory block. The base address and size of

the midrange memory block are programmable. MCS3

is held High during a bus hold condition. In addition,

this pin has a weak internal pullup resistor that is active

during reset.

RFSH—This pin provides a signal timed for auto re-

fresh to PSRAM devices. It is only enabled to function

as a refresh pulse when the PSRAM mode bit is set in

the LMCS Register. An active Low pulse is generated

for 1.5 clock cycles with an adequate deassertion pe-

riod to ensure that overall auto refresh cycle time is

met. This pin is not three-stated during a bus hold condi-

tion.

MCS2–MCS0

(MCS2/PIO24, MCS1/PIO15, MCS0/PIO14)

Midrange Memory Chip Selects (output,

synchronous, internal pullup)

These pins indicate to the system that a memory ac-

cess is in progress to the corresponding region of the

midrange memory block. The base address and size of

the midrange memory block are programmable.

MCS2–MCS0 are held High during a bus hold condi-

tion. In addition, they have weak internal pullup resis-

tors that are active during reset.

NMI

Nonmaskable Interrupt (input, synchronous, edge-

sensitive)

This pin indicates to the microcontroller that an inter-

rupt request has occurred. The NMI signal is the high-

est priority hardware interrupt and, unlike the INT4–

INT0 pins, cannot be masked. The microcontroller al-

ways transfers program execution to the location spec-

ified by the nonmaskable interrupt vector in the

microcontroller interrupt vector table when NMI is as-

serted.

Although NMI is the highest priority interrupt source, it

does not participate in the priority resolution process of

the maskable interrupts. There is no bit associated with

NMI in the interrupt in-service or interrupt request reg-

isters. This means that a new NMI request can interrupt

an executing NMI interrupt service routine. As with all

hardware interrupts, the IF (interrupt flag) is cleared

when the processor takes the interrupt, disabling the

maskable interrupt sources. However, if maskable in-

terrupts are re-enabled by software in the NMI interrupt

service routine, via the STI instruction for example, the

fact that an NMI is currently in service will not have any

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