AM186EM-33VCSLASHW datasheet(32/98 Pages) AMD

32 / 98 page

Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINA R Y

SCLK/PIO20

Serial Clock (output, synchronous)

This pin supplies the synchronous serial interface (SSI)

clock to a slave device, allowing transmit and receive

operations to be synchronized between the microcon-

troller and the slave. SCLK is derived from the micro-

controller internal clock and then divided by 2, 4, 8, or

16 depending on register settings.

An access to any of the SSR or SSD registers activates

SCLK for eight SCLK cycles (see Figure 11 and Figure

12 on page 49). When SCLK is inactive, it is held High

by the microcontroller.

SDATA/PIO21

Serial Data (input/output, synchronous)

This pin transmits synchronous serial interface (SSI)

data to and from a slave device. When SDATA is inac-

tive, a weak keeper holds the last value of SDATA on

the pin.

SDEN1/PIO23, SDEN0/PIO22

Serial Data Enables (output, synchronous)

These pins enable data transfers on port 1 and port 0

of the synchronous serial interface (SSI). The micro-

controller asserts either SDEN1 or SDEN0 at the be-

ginning of a transfer and deasserts it after the transfer

is complete. When SDEN1–SDEN0 are inactive, they

are held Low by the microcontroller.

SRDY/PIO6

Synchronous Ready (input, synchronous,

level-sensitive)

This pin indicates to the microcontroller that the ad-

dressed memory space or I/O device will complete a

data transfer. The SRDY pin accepts an active High

input synchronized to CLKOUTA.

Using SRDY instead of ARDY allows a relaxed system

timing because of the elimination of the one-half clock

period required to internally synchronize ARDY. To al-

ways assert the ready condition to the microcontroller,

tie SRDY High. If the system does not use SRDY, tie

the pin Low to yield control to ARDY.

TMRIN0/PIO11

Timer Input 0 (input, synchronous, edge-sensitive)

This pin supplies a clock or control signal to the internal

microcontroller timer 0. After internally synchronizing a

Low-to-High transition on TMRIN0, the microcontroller

increments the timer. TMRIN0 must be tied High if not

being used.

TMRIN1/PIO0

Timer Input 1 (input, synchronous, edge-sensitive)

This pin supplies a clock or control signal to the internal

microcontroller timer 1. After internally synchronizing a

Low-to-High transition on TMRIN1, the microcontroller

increments the timer. TMRIN1 must be tied High if not

being used.

TMROUT0/PIO10

Timer Output 0 (output, synchronous)

This pin supplies the system with either a single pulse

or a continuous waveform with a programmable duty

cycle. TMROUT0 is floated during a bus hold or reset.

TMROUT1/PIO1

Timer Output 1 (output, synchronous)

This pin supplies the system with either a single pulse

or a continuous waveform with a programmable duty

cycle. TMROUT1 can also be programmed as a watch-

dog timer. TMROUT1 is floated during a bus hold or re-

set.

TXD/PIO27

Transmit Data (output, asynchronous)

This pin supplies asynchronous serial transmit data to

the system from the internal UART of the microcontrol-

ler.

UCS/ONCE1

Upper Memory Chip Select (output, synchronous)

ONCE Mode Request 1 (input, internal pullup)

UCS—This pin indicates to the system that a memory

access is in progress to the upper memory block. The

base address and size of the upper memory block are

programmable up to 512 Kbytes. UCS is held High dur-

ing a bus hold condition.

After power-on reset, UCS is asserted because the pro-

cessor begins executing at FFFF0h and the default config-

uration for the UCS chip select is 64 Kbytes from F0000h

to FFFFFh.

ONCE1—During reset, this pin and ONCE0 indicate to

the microcontroller the mode in which it should operate.

ONCE0 and ONCE1 are sampled on the rising edge of

RES. If both pins are asserted Low, the microcontroller

enters ONCE mode. Otherwise, it operates normally. In

ONCE mode, all pins assume a high-impedance state

and remain in that state until a subsequent reset oc-

curs. To guarantee that the microcontroller does not in-

advertently enter ONCE mode, ONCE1 has a weak

internal pullup resistor that is active only during a reset.

This pin is not three-stated during a bus hold condition.

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