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AM186EM-33VC/W Scheda tecnica(PDF) 66 Page - Advanced Micro Devices |
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AM186EM-33VC/W Scheda tecnica(HTML) 66 Page - Advanced Micro Devices |
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66 / 98 page  66 Am186/188EM and Am186/188EMLV Microcontrollers PRELIMINA R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Write Cycle (20 MHz and 25 MHz) Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals. Preliminary Parameter 20 MHz 25 MHz No. Symbol Description Min Max Min Max Unit General Timing Responses 3 tCHSV Status Active Delay 0 25 0 20 ns 4 tCLSH Status Inactive Delay 0 25 0 20 ns 5 tCLAV AD Address Valid Delay and BHE 0 25 0 20 ns 6 tCLAX Address Hold 0 25 0 20 ns 7 tCLDV Data Valid Delay 0 25 0 20 ns 8 tCHDX Status Hold Time 0 0 ns 9 tCHLH ALE Active Delay 25 20 ns 10 tLHLL ALE Width tCLCL–10= 40 tCLCL–10= 30 ns 11 tCHLL ALE Inactive Delay 25 20 ns 12 tAVLL AD Address Valid to ALE Low(a) tCLCH tCLCH ns 13 tLLAX AD Address Hold from ALE Inactive(a) tCHCL tCHCL ns 14 tAVCH AD Address Valid to Clock High 0 0 ns 16 tCLCSV MCS/PCS Active Delay 0 25 0 20 ns 17 tCXCSX MCS/PCS Hold from Command Inactive(a) tCLCH tCLCH ns 18 tCHCSX MCS/PCS Inactive Delay 0 25 0 20 ns 19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns 20 tCVCTV Control Active Delay 1(b) 0 25 0 20 ns 22 tCHCTV Control Active Delay 2 0 25 0 20 ns 23 tLHAV ALE High to Address Valid 20 15 ns Write Cycle Timing Responses 30 tCLDOX Data Hold Time 0 0 ns 31 tCVCTX Control Inactive Delay(b) 0 25 0 20 ns 32 tWLWH WR Pulse Width 2tCLCL–10 =90 2tCLCL–10 =70 ns 33 tWHLH WR Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns 34 tWHDX Data Hold after WR(a) tCLCL–10= 40 tCLCL–10= 30 ns 35 tWHDEX WR Inactive to DEN Inactive (a) tCLCH–3 tCLCH–3 ns 65 tAVWL A Address Valid to WR Low tCLCL+tCHCL –3 tCLCL+tCHCL –3 ns 67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 25 0 20 ns 68 tCHAV CLKOUTA High to A Address Valid 0 25 0 20 ns 87 tAVBL A Address Valid to WHB, WLB Low tCHCL–3 25 tCHCL–3 20 ns |
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