AM186EM-33VCSLASHW datasheet(31/98 Pages) AMD

31 / 98 page

Am186/188EM and Am186/188EMLV Microcontrollers

P R E L IMINAR Y

Read Strobe (output, synchronous, three-state)

This pin indicates to the system that the microcontroller

is performing a memory or I/O read cycle. RD is guar-

anteed not to be asserted before the address and data bus

is floated during the address-to-data transition. RD floats

during a bus hold condition.

RES

Reset (input, asynchronous, level-sensitive)

This pin requires the microcontroller to perform a reset.

When RES is asserted, the microcontroller immediately

terminates its present activity, clears its internal logic, and

CPU control is transferred to the reset address FFFF0h.

RES must be held Low for at least 1 ms.

RES can be asserted asynchronously to CLKOUTA

because RES is synchronized internally. For proper ini-

tialization, VCC must be within specifications, and CLK-

OUTA must be stable for more than four CLKOUTA

periods during which RES is asserted.

The microcontroller begins fetching instructions ap-

proximately 6.5 CLKOUTA periods after RES is deas-

serted. This input is provided with a Schmitt trigger to

facilitate power-on RES generation via an RC network.

RFSH2/ADEN

(Am188EM Microcontroller Only)

Refresh 2 (three-state, output, synchronous)

Address Enable (input, internal pullup)

RFSH2—Asserted Low to signify a DRAM refresh bus

cycle. The use of RFSH2/ADEN to signal a refresh is

not valid when PSRAM mode is selected. Instead, the

MCS3/RFSH signal is provided to the PSRAM.

ADEN—If RFSH2/ADEN is held High or left floating on

power-on reset, the AD bus (AO15–AO8 and AD7–

AD0) is enabled or disabled during the address portion

of LCS and UCS bus cycles based on the DA bit in the

LMCS and UMCS registers. If the DA bit is set, the

memory address is accessed on the A19–A0 pins. This

mode of operation reduces power consumption. For

more information, see the “Bus Operation” section on

page 37. There is a weak internal pullup resistor on

RFSH2/ADEN so no external pullup is required.

If RFSH2/ADEN is held Low on power-on reset, the AD

bus drives both addresses and data regardless of the DA

bit setting. The pin is sampled one crystal clock cycle after

the rising edge of RES. RFSH2/ADEN is three-stated

during bus holds and ONCE mode.

RXD/PIO28

Receive Data (input, asynchronous)

This pin supplies asynchronous serial receive data

from the system to the internal UART of the microcon-

troller.

S2–S0

Bus Cycle Status (output, three-state,

synchronous)

These pins indicate to the system the type of bus cycle

in progress. S2 can be used as a logical memory or I/O

indicator, and S1 can be used as a data transmit or receive

indicator. S2–S0 float during bus hold and hold acknowl-

edge conditions. The S2–S0 pins are encoded as shown

in Table 4.

Table 4.

Bus Cycle Encoding

S6/CLKDIV2/PIO29

Bus Cycle Status Bit 6 (output, synchronous)

Clock Divide by 2 (input, internal pullup)

S6—During the second and remaining periods of a

cycle (t2, t3, and t4), this pin is asserted High to indicate

a DMA-initiated bus cycle. During a bus hold or reset

condition, S6 floats.

CLKDIV2—If S6/CLKDIV2/PIO29 is held Low during

power-on reset, the chip enters clock divided by 2

mode where the processor clock is derived by dividing

the external clock input by 2. If this mode is selected,

the PLL is disabled. The pin is sampled on the rising

edge of RES.

If S6 is to be used as PIO29 in input mode, the device

driving PIO29 must not drive the pin Low during power-

on reset. S6/CLKDIV2/PIO29 defaults to a PIO input with

pullup, so the pin does not need to be driven High exter-

nally.

Bus Cycle

Interrupt acknowledge

Read data from I/O

Write data to I/O

Halt

Instruction fetch

Read data from memory

Write data to memory

None (passive)

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