AM186EM-33VCSLASHW datasheet(43/98 Pages) AMD

43 / 98 page

Am186/188EM and Am186/188EMLV Microcontrollers

P R E L IMINAR Y

CHIP-SELECT UNIT

The Am186EM and Am188EM microcontrollers con-

tain logic that provides programmable chip-select gen-

eration for both memories and peripherals. The logic

can be programmed to provide ready and wait-state

generation and latched address bits A1 and A2. The

chip-select lines are active for all memory and I/O cy-

cles in their programmed areas, whether they are gen-

erated by the CPU or by the integrated DMA unit.

The Am186EM and Am188EM microcontrollers pro-

vide six chip-select outputs for use with memory de-

vices and six more for use with peripherals in either

memory space or I/O space. The six chip selects for

memory devices can be used to address three memory

ranges. Each of the six peripheral chip selects ad-

dresses a 256-byte block that is offset from a program-

mable base address. A read or write access to the

corresponding chip select register activates the chip

selects.

Chip-Select Timing

The timing for the UCS and LCS outputs is modified from

the original 80C186 microcontroller. These outputs now

assert in conjunction with the nonmultiplexed address bus

for normal memory timing. To allow these outputs to be

available earlier in the bus cycle, the number of program-

mable memory size selections has been reduced.

Ready and Wait-State Programming

The Am186EM and Am188EM microcontrollers can be

programmed to sense a ready signal for each of the pe-

ripheral or memory chip-select lines. The ready signal

can be either the ARDY or SRDY signal. Each chip-se-

lect control register (UMCS, LMCS, MMCS, PACS, and

MPCS) contains a single-bit field that determines

whether the external ready signal is required or ig-

nored.

The number of wait states to be inserted for each ac-

cess to a peripheral or memory region is programma-

ble. The chip-select control registers for UCS, LCS,

MCS3–MCS0, PCS6, and PCS5 contain a two-bit field

that determines the number of wait states from zero to

three to be inserted. PCS3–PCS0 use three bits to pro-

vide additional values of 5, 7, 9, and 15 wait states.

When external ready is required, internally pro-

grammed wait states will always complete before ex-

ternal ready can terminate or extend a bus cycle. For

example, if the internal wait states are set to insert two

wait states, the processor samples the external ready

pin during the first wait cycle. If external ready is as-

serted at that time, the access completes after six cy-

cles (four cycles plus two wait states). If external ready

is not asserted during the first wait state, the access is

extended until ready is asserted, which is followed by

one more wait state followed by t4.

Chip-Select Overlap

Although programming the various chip selects on the

Am186EM and Am188EM microcontrollers so that mul-

tiple chip select signals are asserted for the same

physical address is not recommended, it may be un-

avoidable in some systems. In such systems, the chip

selects whose assertions overlap must have the same

configuration for ready (external ready required or not

required) and the number of wait states to be inserted

into the cycle by the processor.

The peripheral control block (PCB) is accessed using

internal signals. These internal signals function as chip

selects configured with zero wait states and no external

ready. Therefore, the PCB can be programmed to ad-

dresses that overlap external chip select signals if

those external chip selects are programmed to zero

wait states with no external ready required.

When overlapping an additional chip select with either

the LCS or UCS chip selects, it must be noted that set-

ting the Disable Address (DA) bit in the LMCS or UMCS

the AD bus for all accesses for which the associated

chip select is asserted, including any accesses for

which multiple chip selects assert.

The MCS and PCS chip select pins can be configured

as either chip selects (normal function) or as PIO inputs

or outputs. It should be noted; however, that the ready

and wait state generation logic for these chip selects is

in effect regardless of their configurations as chip se-

lects or PIOs. This means that if these chip selects are

enabled (by a read or write to the MMCS and MPCS for

the MCS chip selects, or by a read or write to the PACS

and MPCS registers for the PCS chip selects), the

ready and wait state programming for these signals

must agree with the programming for any other chip se-

lects with which their assertion would overlap if they

were configured as chip selects.

Although the PCS4 signal is not available on an exter-

nal pin, the ready and wait state logic for this signal still

exists internal to the part. For this reason, the PCS4 ad-

dress space must follow the rules for overlapping chip

selects. The ready and wait-state logic for PCS6–

PCS5 is disabled when these signals are configured as

address bits A2–A1.

Failure to configure overlapping chip selects with the

same ready and wait state requirements may cause

the processor to hang with the appearance of waiting

for a ready signal. This behavior may occur even in a

system in which ready is always asserted (ARDY or

SRDY tied High).

AM186EM-33VC/W Scheda tecnica(PDF) 43 Page - Advanced Micro Devices

AM186EM-33VC/W Scheda tecnica(HTML) 43 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

Scheda tecnica Scarica

Link URL