AM186EM-33VCSLASHW datasheet(40/98 Pages) AMD

40 / 98 page

Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINA R Y

Figure 7.

Peripheral Control Block Register Map (continued)

Offset

(Hexadecimal)

INT2 Control Register

INT1 Control Register

INT0 Control Register

DMA 1 Interrupt Control Register

DMA 0 Interrupt Control Register

Timer Interrupt Control Register

Interrupt Status Register

Interrupt Request Register

In-service Register

Priority Mask Register

Interrupt Mask Register

Poll Status Register

Poll Register

End-of-Interrupt Register

Interrupt Vector Register

Synchronous Serial Transmit 1 Register

PIO Mode 0 Register

Changed from 80C186

microcontroller.

Note: Gaps in offset addresses indicate

reserved registers.

Timer 2 Mode/Control Register

Timer 2 Maxcount Compare A Register

Timer 2 Count Register

Timer 1 Mode/Control Register

Timer 1 Maxcount Compare B Register

Timer 1 Maxcount Compare A Register

Timer 1 Count Register

Timer 0 Mode/Control Register

Timer 0 Maxcount Compare B Register

Timer 0 Maxcount Compare A Register

Timer 0 Count Register

INT3 Control Register

PIO Data 1 Register

PIO Direction 1 Register

PIO Mode 1 Register

PIO Data 0 Register

PIO Direction 0 Register

Serial Port Interrupt Control Register

Watchdog Timer Control Register

INT4 Control Register

Synchronous Serial Receive Register

Synchronous Serial Transmit 0 Register

Synchronous Serial Enable Register

Synchronous Serial Status Register

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