AM186EM-33VCSLASHW datasheet(45/98 Pages) AMD

45 / 98 page

Am186/188EM and Am186/188EMLV Microcontrollers

P R E L IMINAR Y

REFRESH CONTROL UNIT

The Refresh Control Unit (RCU) automatically gener-

ates refresh bus cycles. After a programmable period

of time, the RCU generates a memory read request to

the bus interface unit. The RCU is fixed to three wait

states for the PSRAM auto refresh mode.

If the HLDA pin is active when a refresh request is gen-

erated (indicating a bus hold condition), then the

Am186EM and Am188EM microcontrollers deactivate

the HLDA pin in order to perform a refresh cycle. The

external bus master must remove the HOLD signal for

at least one clock in order to allow the refresh cycle to

execute. The sequence of HLDA going inactive while

HOLD is being held active can be used to signal a

pending refresh request.

INTERRUPT CONTROL UNIT

The Am186EM and Am188EM microcontrollers can re-

ceive interrupt requests from a variety of sources, both

internal and external. The internal interrupt controller

arranges these requests by priority and presents them

one at a time to the CPU.

There are six external interrupt sources on the

Am186EM and Am188EM microcontrollers—five

maskable interrupt pins and one nonmaskable interrupt

pin. In addition, there are six total internal interrupt

sources—three timers, two DMA channels, and the

asynchronous serial port—that are not connected to

external pins.

The Am186EM and Am188EM microcontrollers pro-

vide three interrupt sources not present on the Am186

and Am188 microcontrollers. The first is an additional

external interrupt pin (INT4). This pin operates much

like the already existing interrupt pins (INT3–INT0).

The second is an internal watchdog timer interrupt. The

third is an internal interrupt from the asynchronous se-

rial port.

The five maskable interrupt request pins can be used

as direct interrupt requests, or they can be cascaded

with an 82C59A-compatible external interrupt control-

ler if more inputs are needed. An external interrupt con-

tr ol l e r c an be u s ed as the s ys t e m m a s t e r by

programming the internal interrupt controller to operate

in slave mode. In all cases, nesting can be enabled so

that interrupt service routines for lower priority inter-

rupts are interrupted by a higher priority interrupt.

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