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AM186EM-33VC/W Scheda tecnica(PDF) 73 Page - Advanced Micro Devices |
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AM186EM-33VC/W Scheda tecnica(HTML) 73 Page - Advanced Micro Devices |
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73 / 98 page  Am186/188EM and Am186/188EMLV Microcontrollers 73 P R E L IMINAR Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range PSRAM Write Cycle (33 MHz and 40 MHz) Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, WR, WHB, and WLB signals. Preliminary Parameter 33 MHz 40 MHz No. Symbol Description Min Max Min Max Unit General Timing Responses 5 tCLAV AD Address Valid Delay and BHE 0 15 0 12 ns 7 tCLDV Data Valid Delay 0 15 0 12 ns 8 tCHDX Status Hold Time 0 0 ns 9 tCHLH ALE Active Delay 15 12 ns 10 tLHLL ALE Width tCLCL–10=20 tCLCL–5=20 ns 11 tCHLL ALE Inactive Delay 15 12 ns 20 tCVCTV Control Active Delay 1(b) 0 15 0 12 ns 23 tLHAV ALE High to Address Valid 10 7.5 ns 80 tCLCLX LCS Inactive Delay 0 15 0 12 ns 81 tCLCSL LCS Active Delay 0 15 0 12 ns 84 tLRLL LCS Precharge Pulse Width tCLCL + tCLCH –3 tCLCL + tCLCH –1.25 Write Cycle Timing Responses 30 tCLDOX Data Hold Time 0 0 ns 31 tCVCTX Control Inactive Delay(b) 0 15 0 12 ns 32 tWLWH WR Pulse Width 2tCLCL–10 =50 2tCLCL–10 =40 ns 33 tWHLH WR Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns 34 tWHDX Data Hold after WR(a) tCLCL–10=20 tCLCL–10=15 ns 65 tAVWL A Address Valid to WR Low tCLCL+tCHCL –3 tCLCL+tCHCL –1.25 ns 68 tCHAV CLKOUTA High to A Address Valid 0 15 0 10 ns 87 tAVBL A Address Valid to WHB, WLB Low tCHCL–3 15 tCHCL–1.25 12 ns |
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