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AM186EM-33VC/W Scheda tecnica(PDF) 64 Page - Advanced Micro Devices |
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AM186EM-33VC/W Scheda tecnica(HTML) 64 Page - Advanced Micro Devices |
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64 / 98 page  64 Am186/188EM and Am186/188EMLV Microcontrollers PRELIMINA R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Read Cycle (33 MHz and 40 MHz) Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals. c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. Preliminary Parameter 33 MHz 40 MHz No. Symbol Description Min Max Min Max Unit General Timing Requirements 1 tDVCL Data in Setup 8 5 ns 2 tCLDX Data in Hold(c) 3 2 ns General Timing Responses 3 tCHSV Status Active Delay 0 15 0 12 ns 4 tCLSH Status Inactive Delay 0 15 0 12 ns 5 tCLAV AD Address Valid Delay and BHE 0 15 0 12 ns 6 tCLAX Address Hold 0 25 0 20 ns 7 tCLDV Data Valid Delay 0 15 0 12 ns 8 tCHDX Status Hold Time 0 0 ns 9 tCHLH ALE Active Delay 15 12 ns 10 tLHLL ALE Width tCLCL–10=20 tCLCL–5 =20 ns 11 tCHLL ALE Inactive Delay 15 12 ns 12 tAVLL AD Address Valid to ALE Low(a) tCLCH –2 tCLCH –2 ns 13 tLLAX AD Address Hold from ALE Inactive(a) tCHCL–2 tCHCL –2 ns 14 tAVCH AD Address Valid to Clock High 0 0 ns 15 tCLAZ AD Address Float Delay tCLAX=0 15 tCLAX=0 12 ns 16 tCLCSV MCS/PCS Active Delay 0 15 0 12 ns 17 tCXCSX MCS/PCS Hold from Command Inactive(a) tCLCH–2 tCLCH–2 ns 18 tCHCSX MCS/PCS Inactive Delay 0 15 0 12 ns 19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns 20 tCVCTV Control Active Delay 1(b) 0 15 0 12 ns 21 tCVDEX DEN Inactive Delay 0 15 0 12 ns 22 tCHCTV Control Active Delay 2(b) 0 15 0 12 ns 23 tLHAV ALE High to Address Valid 10 7.5 ns Read Cycle Timing Responses 24 tAZRL AD Address Float to RD Active 0 0 ns 25 tCLRL RD Active Delay 0 15 0 10 ns 26 tRLRH RD Pulse Width 2tCLCL–15=45 2tCLCL–10=40 ns 27 tCLRH RD Inactive Delay 0 15 0 12 ns 28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–2 ns 29 tRHAV RD Inactive to AD Address Active(a) tCLCL–10=20 tCLCL–5 =20 ns 59 tRHDX RD High to Data Hold on AD Bus(c) 0 0 ns 66 tAVRL A Address Valid to RD Low(a) 2tCLCL–15=45 2tCLCL–10=40 ns 67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 15 0 10 ns 68 tCHAV CLKOUTA High to A Address Valid 0 15 0 10 ns |
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