AM186EM-33VCSLASHW datasheet(37/98 Pages) AMD

37 / 98 page

Am186/188EM and Am186/188EMLV Microcontrollers

P R E L IMINAR Y

Figure 6.

Am188EM Microcontroller—Read and Write with Address Bus Disable In Effect

BUS INTERFACE UNIT

The bus interface unit controls all accesses to external

peripherals and memory devices. External accesses

include those to memory devices, as well as those to

memory-mapped and I/O-mapped peripherals and the

pe r i pher al cont r o l bloc k. The Am186EM an d

Am188EM microcontrollers provide an enhanced bus

interface unit with the following features:

n A nonmultiplexed address bus

n Separate byte write enables for high and low bytes

in the Am186EM microcontroller only

n Pseudo Static RAM (PSRAM) support

The standard 80C186/188 multiplexed address and

data bus requires system interface logic and an exter-

nal address latch. On the Am186EM and Am188EM

microcontrollers, new byte write enables, PSRAM con-

trol logic, and a new nonmultiplexed address bus can

reduce design costs by eliminating this external logic.

Nonmultiplexed Address Bus

The nonmultiplexed address bus (A19–A0) is valid

one-half CLKOUTA cycle in advance of the address on

the AD bus. When used in conjunction with the modi-

fied UCS and LCS outputs and the byte write enable sig-

nals, the A19–A0 bus provides a seamless interface to

SRAM, PSRAM, and Flash/EPROM memory systems.

Byte Write Enables

The Am186EM microcontroller provides the WHB

(Write High Byte) and WLB (Write Low Byte) signals, which

act as byte write enables.

WHB is the logical OR of BHE and WR. WHB is Low

when BHE and WR are both Low. WLB is the logical

OR of AD0 and WR. WLB is Low when AD0 and WR

are both Low. WB is Low whenever a byte is written on

the Am188EM microcontroller.

The byte write enables are driven in conjunction with

the nonmultiplexed address bus as required for the

write timing requirements of common SRAMs.

CLKOUTA

AD7–AD0

(Read)

Data

Address

AO15–AO8

LCS, UCS

AD7–AD0

(Write)

Data

Address

Phase

Data

Phase

A19–A0

Address

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