AM186EM-33VCSLASHW datasheet(44/98 Pages) AMD

44 / 98 page

Am186/188EM and Am186/188EMLV Microcontrollers

PRELIMINA R Y

Configuring PCS in I/O space with LCS or any other

chip select configured for memory address 0 is not con-

sidered overlapping of the chip selects. Overlapping

chip selects refers to configurations where more than

one chip select asserts for the same physical address.

Upper Memory Chip Select

The Am186EM and Am188EM microcontrollers pro-

vide a UCS chip select for the top of memory. On reset,

the Am186EM and Am188EM microcontrollers begin

fetching and executing instructions starting at memory lo-

cation FFFF0h. Therefore, upper memory is usually used

as instruction memory. To facilitate this usage, UCS de-

faults to active on reset, with a default memory range of 64

Kbytes from F0000h to FFFFFh, with external ready re-

quired and three wait states automatically inserted. The

UCS memory range always ends at FFFFFh. The lower

boundary is programmable.

Low Memory Chip Select

The Am186EM and Am188EM microcontrollers pro-

vide an LCS chip select for the bottom of memory. Since

the interrupt vector table is located at the bottom of mem-

ory starting at 00000h, the LCS pin is usually used to con-

trol data memory. The LCS pin is not active on reset.

Midrange Memory Chip Selects

The Am186EM and Am188EM microcontrollers pro-

vide four chip selects, MCS3–MCS0, for use in a user-

locatable memory block. The base address of the memory

block can be located anywhere within the 1-Mbyte mem-

ory address space, exclusive of the areas associated with

the UCS and LCS chip selects, as well as the address

range of the Peripheral Chip Selects, PCS6, PCS5, and

PCS3–PCS0, if they are mapped to memory. The MCS

address range can overlap the PCS address range if the

PCS chip selects are mapped to I/O space.

Unlike the UCS and LCS chip selects, the MCS outputs

assert with the multiplexed AD address bus.

Peripheral Chip Selects

The Am186EM and Am188EM microcontrollers pro-

vide six chip selects, PCS6–PCS5 and PCS3–PCS0,

for use within a user-locatable memory or I/O block.

PCS4 is not available on the Am186EM and Am188EM

microcontrollers. The base address of the memory

block can be located anywhere within the 1-Mbyte

memory address space, exclusive of the areas associ-

ated with the UCS, LCS, and MCS chip selects, or they

can be configured to access the 64 Kbyte I/O space.

The PCS pins are not active on reset. PCS6–PCS5 can

have from zero to three wait states. PCS3–PCS0 can have

four additional wait-state values—5, 7, 9, and 15.

Unlike the UCS and LCS chip selects, the PCS outputs

assert with the multiplexed AD address bus. Note also that

each peripheral chip select asserts over a 256-byte address

range, which is twice the address range covered by periph-

eral chip selects in the 80C186 and 80C188 microcontrol-

lers.

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