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AM186EM-33VC/W Scheda tecnica(PDF) 90 Page - Advanced Micro Devices |
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AM186EM-33VC/W Scheda tecnica(HTML) 90 Page - Advanced Micro Devices |
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90 / 98 page  90 Am186/188EM and Am186/188EMLV Microcontrollers PRELIMINA R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating range Reset and Bus Hold (20 MHz and 25 MHz) Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a This timing must be met to guarantee recognition at the next clock. Reset and Bus Hold (33 MHz and 40 MHz) Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a This timing must be met to guarantee recognition at the next clock. Preliminary Parameter 20 MHz 25 MHz No. Symbol Description Min Max Min Max Unit Reset and Bus Hold Timing Requirements 5 tCLAV AD Address Valid Delay and BHE 0 25 0 20 ns 15 tCLAZ AD Address Float Delay 0 25 0 20 ns 57 tRESIN RES Setup Time 10 10 ns 58 tHVCL HOLD Setup(a) 10 10 ns Reset and Bus Hold Timing Responses 62 tCLHAV HLDA Valid Delay 0 25 0 20 ns 63 tCHCZ Command Lines Float Delay 25 20 ns 64 tCHCV Command Lines Valid Delay (after Float) 25 20 ns Preliminary Parameter 33 MHz 40 MHz No. Symbol Description Min Max Min Max Unit Reset and Bus Hold Timing Requirements 5 tCLAV AD Address Valid Delay and BHE 0 15 0 12 ns 15 tCLAZ AD Address Float Delay 0 15 0 12 ns 57 tRESIN RES Setup Time 8 5 ns 58 tHVCL HOLD Setup(a) 8 5 ns Reset and Bus Hold Timing Responses 62 tCLHAV HLDA Valid Delay 0 15 0 12 ns 63 tCHCZ Command Lines Float Delay 15 12 ns 64 tCHCV Command Lines Valid Delay (after Float) 15 12 ns |
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