PTN3355

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© NXP Semiconductors N.V. 2016. All rights reserved.

Product data sheet

Rev. 3.1 — 4 November 2016

2 of 37

NXP Semiconductors

PTN3355

Low power DP to VGA adapter with integrated 1 : 2 VGA switch

2.3 DDC channel output

 I2C-Over-AUX feature facilitates support of MCCS, DDC/CI, and DDC protocols (see

Ref. 2)

2.4 Analog video output

 VSIS 1.2 compliance (Ref. 3) for supported video output modes

 Analog RGB current-source outputs

 3.3 V VSYNC and HSYNC outputs

 Pixel clock up to 240 MHz

 Triple 8-bit Digital-to-Analog Converter (DAC)

 Direct drive of double terminated 75

 load with standard 700 mV (peak-to-peak)

signals

 Integrated 1 : 2 VGA switch

2.5 General features

 Supports firmware upgradability through ‘Flash-over-AUX’ scheme for Windows

 Supports firmware upgradability through I2C-bus interface

 Monitor presence detection through load detection scheme. Connection/disconnection

reported via HPD IRQ and DPCD update.

 Wide set of display resolutions are supported1:

 1920

 1440, 60 Hz, 18 bpp, 234 MHz pixel clock rate

 2048

 1152, 60 Hz (reduced blanking), 24 bpp, 162 MHz pixel clock rate

 2048

 1536, 50 Hz (reduced blanking), 24 bpp, 167.2 MHz pixel clock rate

 WUXGA: 1920

 1200, 60 Hz, 18 bpp, 193 MHz pixel clock rate

 WUXGA: 1920

 1200, 60 Hz (reduced blanking), 24 bpp, 154 MHz pixel clock rate

 UXGA: 1600

 1200, 60 Hz, 162 MHz pixel clock rate

 SXGA: 1280

 1024, 60 Hz, 108 MHz pixel clock rate

 XGA: 1024

 768, 60 Hz, 65 MHz pixel clock rate

 SVGA: 800

 600, 60 Hz, 40 MHz pixel clock rate

 VGA: 640

 480, 60 Hz, 25 MHz pixel clock rate

 Any resolution and refresh rates are supported from 25 MHz up to 180 MHz pixel

clock rate at 24 bpp, or up to 240 MHz pixel clock rate at 18 bpp

 Bits per color (bpc) supported1

 6, 8 bits supported

 10, 12, 16 bits supported by truncation to 8 MSBs

 All VGA colorimetry formats (RGB) supported

 Power modes (when the application design is as per Figure 4)

 Active-mode power consumption: ~200 mW at WUXGA, 1920

 1200, 60 Hz

(18 bpc)

 410

W at Low-power mode

 Supports slave I2C-bus interface for host debugging and configuration

1.

Except for color depth beyond 8 bits, display resolutions and refresh rates are only limited to those which a standard 2-lane

DisplayPort configuration is able to support over 2.7 Gbit/s per lane of DP Main Link.