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PTN3355

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Product data sheet

Rev. 3.1 — 4 November 2016

11 of 37

NXP Semiconductors

PTN3355

Low power DP to VGA adapter with integrated 1 : 2 VGA switch

Power-up and reset

PTN3355 has built-in power-on reset circuitry which automatically sequences the part

through reset and initialization. In addition, there is a dedicated pin (RST_N) to

control/effect reset operation externally. This provides flexibility at the platform level for

debug or application purpose.

Before link is established, the PTN3355 holds VSYNC and HSYNC signals LOW and

blanks the RGB signals.

While the PTN3355 performs power-on initialization,

• The HPD signal is driven LOW, to indicate to the DisplayPort source that the

PTN3355 is not ready for AUX channel communication. Once the device is initialized,

the HPD level is produced based on CFG1_SCL/CFG2_SDA setting

• The RGB outputs are disabled

• The VSYNC and HSYNC outputs are maintained LOW as long as there is no active

video streaming from the DisplayPort source.

Configurability and programmability

The PTN3355 delivers flexibility for application usage by providing configurability via two

options:

• Configuration pins CFG1_SCL, CFG2_SDA, CFG5, DOCK_IN and TESTMODE

• DP-AUX vendor-specific configuration registers

The pins provide limited application board level configurability, whereas vendor-specific

configuration registers deliver ultimate flexibility. The configuration pin changes (static,

dynamic) are reflected in the IC behavior.

The configuration pin definitions are as follows:

• CFG1_SCL, CFG2_SDA are used for either host I2C communication or as dedicated

configuration pins with binary leveled I/O. PTN3355 is flexible to accept either. The

use of these configuration pins is defined in Table 8.

• Configuration pin CFG5 selects OSC_IN clock frequency setting. Table 5 captures the

pin definition.

Table 6 captures DOCK_IN pin definition.

Table 5.

CFG5 pin definition

Configuration input

OSC_IN clock frequency setting

LOW

25 MHz

HIGH

33 MHz

open

27 MHz

Table 6.

DOCK_IN pin definitions

Configuration input

VGA active output

LOW

channel 1

HIGH

channel 2

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