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F4MP Scheda tecnica(PDF) 10 Page - NXP Semiconductors

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Spiegazioni elettronici  Low power DisplayPort to VGA adapter with integrated 1 : 2 VGA switch
PDF  37 Pages
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Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

F4MP Scheda tecnica(HTML) 10 Page - NXP Semiconductors

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PTN3355
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 4 November 2016
10 of 37
NXP Semiconductors
PTN3355
Low power DP to VGA adapter with integrated 1 : 2 VGA switch
7.4 VGA monitor detection
The PTN3355 implements a robust scheme for VGA monitor detection. It senses
presence or absence of VGA monitor load termination (75
) by pulsing the RGB lines.
The load sensing operation is performed periodically to determine the latest VGA
connectivity status. If the VGA monitor is disconnected, then the detection logic informs
the host platform via IRQ_HPD signal.
7.5 EDID handling
Figure 3 shows a DisplayPort-to-analog video converter between the DisplayPort source
and a VGA monitor. The PTN3355 implements a DP I2C-Over-AUX protocol, providing for
DP source access to the monitor’s DDC bus. With this, the monitor’s EDID data is made
available to DP source for access at any time.
It is the responsibility of the source to choose only video modes which are declared in the
EDID and to adjust the DisplayPort link capabilities (link rate and lane count) to provide
the necessary video bandwidth. The PTN3355 does not cache or modify the EDID to
match the capabilities of the DisplayPort link data.
If the DisplayPort source drives display modes that are not specified in the EDID mode
list, the PTN3355 does not detect such conditions, and it depends entirely on the VGA
display on what is being displayed.
7.6 Triple 8-bit video DACs and VGA outputs
The triple 8-bit video DACs output a 700 mV (peak-to-peak) analog video output signal
into 37.5
 load, as is the case of a doubly terminated 75  cable. The DAC is capable of
supporting the maximum pixel rate supported by a two-lane DP link (240 MHz).
7.6.1 DAC reference resistor
An external reference resistor must be connected between pin RSET and ground. This
resistor sets the reference current which determines the analog output level, and is
specified as 1.2 k
 with a 1 % tolerance. This value allows a 0.7 V (peak-to-peak) output
into a 37.5
 load (for example, double-terminated 75  coaxial cable).
Fig 3.
DisplayPort to VGA adapter IC sits between the DisplayPort source and a VGA
monitor with EDID
DP Tx
002aaf640
embedded
DisplayPort
source device
DP Rx
with DPCD
VIDEO DAC
DisplayPort to VGA adapter IC
box-to-box
legacy
VGA DISPLAY
WITH EDID
sink device



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