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F4MP Scheda tecnica(PDF) 13 Page - NXP Semiconductors |
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F4MP Scheda tecnica(HTML) 13 Page - NXP Semiconductors |
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13 / 37 page ![]() xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Parts shown with shading are extra components required in DC-to-DC converter mode to achieve low power performance. Fig 4. Application with DC-to-DC converter mode 002aah568 PTN3355 VDDE33_IO ML1_P ML1_N DDC_SDA1 VDDA15_DP DDC_SCL2 ML0_N VSYNC1 ML0_P HSYNC1 VDDE33_IO BLU1 AUX_N BLU2 AUX_P GRN1 DOCK_IN GRN2 VDDA33_DNW RSET 10 21 922 823 724 625 526 427 328 229 130 RED HPD ML1_P ML1_N ML0_N ML0_P AUX_N AUX_P 0.01 μF VBUCK_1V5 0.1 μF VDD_3V3 0.1 μF VDD_3V3 DDC_SCL 0.1 μF VDD_3V3 DDC_SDA VSYNC_VGA HSYNC_VGA BLU GRN 1.2 kΩ ± 1 % 0.1 μF 27 MHz 0.1 μF 4.7 μF VBUCK_1V5 1 μF (optional) 0.1 μF 2.2 μF VDD_3V3 +3.3 V FB CFG1, CFG2: 11, default 00, if MS bus is not used 10 kΩ 36 Ω 36 Ω 0.1 μF 0.1 μF ML0_N ML0_P 0.1 μF 0.1 μF ML1_N ML1_P 0.1 μF 0.1 μF AUX_N AUX_P 100 kΩ HPD CPU/GPU +3.3 V VDD_5V (optional) MS_SDA_CFG2 MS_SCL_CFG1 Assume SM_BUS has pull-up on system side. Resonator (with built-in capacitors) MS_SDA_CFG2 MS_SCL_CFG1 CFG5_XTAL CFG5 open: 27 MHz XTAL is used CFG3 CFG3 open: not used 2 kΩ 2 kΩ DDC1_PU BAT54 VDD_5V Option design: ESD protection circuitry RED_RTN NC1 RED GREEN_RTN SDA GREEN BLU_RTN HS BLUE +5V VS NC2 GND1 SCL GND2 GND3 GND4 VGA_CONN 16 17 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 VDD_CONN_5V RED_VGA DDC_SDA GRN_VGA HSYNC_VGA BLU_VGA VSYNC_VGA DDC_SCL BAT54 VDD_5V 22 Ω; 300 mA 22 Ω; 300 mA 22 Ω; 300 mA PI filter design is customer specific RED_VGA DNL 3.3 pF GRN_VGA BLU_VGA 3.3 pF DNL 3.3 pF 3.3 pF DNL 3.3 pF 3.3 pF 75 Ω 75 Ω 75 Ω RED GRN BLU Header 4 (no load) I2C BIRD PIN OUT 1 2 3 4 Option design MS_I2C MS_SCL_CFG1 MS_SDA_CFG2 1 2 3 4 8 7 6 5 74LVC2T45GN VCCA 1A 2A GND VCCB 1B 2B DIR 0.1 μF HS_5V VS_5V 10 kΩ VDD_3V3 VDD_5V VDD_3V3 0.1 μF HSYNC_VGA VSYNC_VGA Option design: Install to support 5 V H/V for legacy projector and CRTs. Place 100 nF capacitor as close as possible to pin 38 and pin 40 without vias at same side as PTN3355. FB FB FB |
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