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Fig 5.

Application with LDO mode

aaa-010214

PTN3355

VDDE33_IO

ML1_P

ML1_N

DDC_SDA1

VDDA15_DP

DDC_SCL2

ML0_N

VSYNC1

ML0_P

HSYNC1

VDDE33_IO

BLU1

AUX_N

BLU2

AUX_P

GRN1

DOCK_IN

GRN2

VDDA33_DNW

RSET

10

21

922

823

724

625

526

427

328

229

130

U1

RED

HPD

ML1_P

ML1_N

ML0_N

ML0_P

0.1 μF

0.1 μF

VDD_3V3

0.1 μF

VDD_3V3

DDC_SCL

0.1 μF

VDD_3V3

DDC_SDA

VSYNC_VGA

HSYNC_VGA

BLU

GRN

1.2 kΩ ± 1 %

0.1 μF

27 MHz

resonator (with

built-in capacitors)

VDD_3V3

0.1 μF

0.1 μF

ML0_N

ML0_P

0.1 μF

0.1 μF

ML1_N

ML1_P

0.1 μF

0.1 μF

AUX_N

AUX_P

HPD

CPU/GPU

VDD_3V3

CFG1, CFG2:

11, default

00, if MS bus is not used

VDD_5V

36 Ω

36 Ω

AUX_N

AUX_P

MS_SDA_CFG2

MS_SCL_CFG1

CFG5_XTAL

CFG3

2.2 kΩ

2.2 kΩ

VDD_5V

C59

Assume SMBus has pull-up on system side.

C21

C60

C61

C10

C11

MS_SCL_CFG1

MS_SDA_CFG2

CFG3

MS_SCL_CFG1

MS_SDA_CFG2

CFG5_XTAL

TESTMODE

DOCK_IN

TESTMODE open: I2C address = C0h

CFG5 open: 27 MHz XTAL is used

CFG3 open: not used

RED_RTN

NC1

RED

GREEN_RTN

SDA

GREEN

BLU_RTN

HS

BLUE

+5V

VS

NC2

GND1

SCL

GND2

GND3

GND4

VGA_CONN

16

17

6

11

1

7

12

2

8

13

3

9

14

4

10

15

5

VDD_5V

RED

DDC_SDA

GRN

HSYNC_VGA

BLU

VSYNC_VGA

DDC_SCL

RED

GRN

BLU

75 Ω

75 Ω

75 Ω

PI filter

design is

customer

specific

VDDD15

VDD_3V3

2.2 μF

4.7 μF