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PTN3355

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Product data sheet

Rev. 3.1 — 4 November 2016

8 of 37

NXP Semiconductors

PTN3355

Low power DP to VGA adapter with integrated 1 : 2 VGA switch

7.2 DisplayPort auxiliary channel (AUX CH)

The AUX CH is a half-duplex, bidirectional channel between DisplayPort source and sink.

It consists of one differential pair transporting self-clocked data at 1 Mbit/s. The PTN3355

integrates the AUX CH replier (or slave), and responds to transactions initiated by the

DisplayPort source AUX CH requester (or master).

The AUX CH uses the Manchester-II code for the self-clocked transmission of signals;

every ‘zero’ is represented by LOW-to-HIGH transition, and ‘one’ represented by

HIGH-to-LOW transition, in the middle of the bit time.

7.3 DPCD registers

DPCD registers that are part of the VESA DisplayPort standard are described in detail in

Ref. 1. The following describes the specific implementation by PTN3355 only.

PTN3355 DisplayPort receiver capability and status information about the link are

reported by DisplayPort Configuration Data (DPCD) registers, when a DP source issues a

read command on the AUX CH. The DP source device can also write to the link

configuration field of DPCD to configure and initialize the link. The DPCD is DisplayPort

v1.2a compliant.

PTN3355 specific capabilities are made available to DP source in the relevant DPCD

read/write registers. In line with the DisplayPort standard (Ref. 1), the specific Link

controls are also made available to initialize and maintain the DisplayPort Link.

It is the responsibility of the DP source to issue commands only within the capability of the

PTN3355 as defined in the ‘Receiver Capability Field’ in order to prevent undefined

behavior. PTN3355 specific DPCD registers are listed in Table 4.

7.3.1 PTN3355 specific DPCD register settings

Table 4.

PTN3355 specific DPCD registers

DPCD

Description

Power-on

Reset

value

Read/write

over

AUX CH

Receiver Capability Field

0000Ch

I2C-bus speed control capabilities bit map. Speed control is

not supported through DPCD register. Default speed of

50 kbit/s is supported.

00h

read only

0000Dh

eDP_CONFIGURATION_CAP.

Bit 0 = ALTERNATE_SCRAMBLER_RESET_CAPABLE.

A setting of 1 indicates that this is an eDP device that

can use the eDP alternate scrambler reset value of

FFFFh.

Bit 1 = FRAMING_CHANGE_CAPABLE. A setting of 1

indicates that this is an eDP device that uses only

Enhanced Framing independently of the setting by the

source of ENHANCED_FRAME_EN.

Bit 2 = reserved for eDP. Read 0.

Bit 3 = DPCD_DISPLAY_CONTROL_CAPABLE. A

setting of 1 indicates that display control registers

starting at address 00700h are enabled.

Bits 7:4 = reserved for eDP. Read all zeros.

03h

read only

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